The background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition or use of that term provided herein, the definition or use of that term provided herein applies and the definition or use of that term in the reference does not apply.
As hardware companies continually push the performance of their systems and integrated chips (ICs), achieving the required communication bandwidth is becoming increasingly challenging. System level bandwidth requirements have approximately doubled every generation, and keeping pace requires aggressively designing for higher data rates and lane counts. This leads to greater signal densities, more package and board layers, more intricate routing topologies, and increased serializer/deserializer (SerDes) tuning complexity. As a result, properly managing and understanding the complexity and variation in these designs becomes paramount.
For this, designers rely on modeling and simulation. Fast and accurate simulation is a crucial part of the design methodology and affords designers a wealth of opportunities. For example, through accurate simulation, designers can ascertain the impact of critical parameter variations, find trends and explain anomalies during debug, prepare for system bring-up and tuning, and perform proof-of-concept simulations for architecture improvement.
Furthermore, because system design is a collaborative effort between many teams, a notable challenge in the industry is providing a flexible, unified platform to simulate one part of the system with the components designed by the other groups.
Industry has considered or implemented several different alternative simulation solutions. Time-domain simulation (SPICE) is the de facto standard for transistor-level circuit simulation and could be extended into system simulation. In the past, transient simulation with SPICE transmitter and receiver models along with lossy transmission line parameters have been used to generate eye diagrams at the receiver input and then compared to a predefined receiver eye mask.
Frequency-domain simulation tools such as Keysight ADS are available for providing a native way to handle frequency-dependent effects and S-parameters. These tools normally make use of simplified linear driver/receiver models, but many also include support for behavioral modeling through the Input/output Buffer Information Specification-Algorithmic Modeling Interface (IBIS-AMI) standard. The IBIS-AMI specification provides a method to encapsulate SerDes intellectual property (e.g., implementation details, algorithms, etc.) in interoperable, transportable models that cannot be reverse engineered.
Some IC manufacturers have proprietary simulators designed specifically for their own transmitter and receiver devices. Each tool contains built-in models that can accurately describe the SerDes electrical and algorithmic behavior at each end of the link, and the simulator is custom tailored to handle these models. Current methodologies rely on a mix of these existing tools, and it is not uncommon for different teams to be simulating their models with different tools.
However, existing simulation solutions are suboptimal. Transient SPICE simulation is too slow and cannot simulate the millions of bits needed to predict link performance. It is also difficult to incorporate the algorithmic behavior of the transmitter and receiver circuitry, including equalization and clock data recovery. As data rates have increased and signal integrity through the analog channel continues to degrade rapidly, it is no longer sufficient to evaluate the eye without considering the advanced nonlinear equalization techniques used in today's SerDes modules.
Proprietary simulators are inherently limited due to the focus on their own design technologies. This exclusivity is acceptable only if all of the SerDes blocks (e.g., transmitters and receivers) are designed by one vendor. The proprietary tools can apply highly tailored algorithms and significant shortcuts in their solver methods that work well with the known embedded driver/receiver models. The downside is that these models are typically not discrete modules that can be readily substituted or exported; rather, the model representations are interwoven throughout the simulation code. External designs cannot be easily integrated into these simulators, nor can the embedded models be readily ported for use in commercial tools.
Commercial electronic design automation (EDA) tools for link simulation can support IBIS-AMI models, but unfortunately, constructing IBIS-AMI models may require significant development time. From a tool perspective, the black box nature of these IBIS-AMI models means that simulators must follow rigid computational approaches based on the model standards and what data is available externally. In addition, access to intermediate results and internal model data (such as adaptation behavior) is often limited, since the IBIS-AMI specification only stipulates for the output waveform and clock information to be returned from the model. The limitations prevent designers from precisely analyzing the behavior of the individual SerDes blocks and consequently reducing designers' capability to correct and improve on the SerDes designs.
Thus, there remains a need for a system and method that allows testers to efficiently build sophisticated simulation systems for simulating system links that are made up of SerDes blocks designed by different groups of engineers.